(1) Field of the Invention
The invention relates to the fabrication of integrated circuit device, and more particularly, to a method of creating a copper interconnect without the need for a separate barrier layer.
(2) Description of the Prior Art
In the creation of semiconductor devices, the creation of conductive interconnects has become increasingly more important due to the continuing reduction in device parameters, a reduction that is driven by requirements of improved device performance. Metal is typically used for the creation of conducting interconnects comprising such materials as aluminum, tungsten, titanium copper polysilicon, polycide or alloys of these metal. For the creation of metal interconnects a Ti/TiN/AlCu/TiN process is the preferred method. Electrically conductive materials that can be used for the metal lines include but are not limited to Al, Ti, Ta, W, Mo, Cu, their alloys or a combination of these materials.
Due to increased requirements of low resistance of interconnect metal, copper has become more attractive as a material for the creation of interconnect metal. The invention relates to the fabrication of copper conductive lines and vias that provide the conductive interconnections of integrated circuits in semiconductor devices or the interconnections in a multilayer substrate over the surface of which semiconductor devices are mounted. More particularly, the fabrication of conductive lines and vias using damascene and dual damascene processes.
In fabricating Very and Ultra Large Scale Integration (VLSI and ULSI) circuits with the dual damascene process, an insulating or dielectric material, such as silicon oxide, of a semiconductor device is patterned with several thousand openings for the conductive lines and vias. These openings are filled at the same time with metal and serve to interconnect the active and passive elements of the integrated circuit. The dual damascene process also is used for forming multilevel conductive lines of metal, such as copper, in layers of insulating material, such as polyimide, of multi-layer substrates over which semiconductor devices are mounted.
Damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in addition to forming the grooves of single damascene, conductive via openings also are formed. In the standard dual damascene process, the insulating layer is coated with a layer of photoresist, which is exposed through a first mask with an image pattern of via openings, the via pattern is anisotropically etched in the upper half of the insulating layer. The photoresist now is exposed through a second mask with an image pattern of the conductive line openings or trenches, after being aligned with the first mask of the via pattern to encompass the via openings. By anisotropically etching the openings for the conductive lines in the upper half of the insulating material, the via openings already present in the upper half of insulating material are simultaneously etched and replicated in the lower half of the insulating material. After the etching is complete, both the vias and line openings are filled with metal. Dual damascene is an improvement over single damascene because it permits the filling of both the conductive grooves and vias with metal at the same time, thereby eliminating process steps.
Copper is being increasingly used as an interconnect metal due to its low cost and low resistivity. Copper however has a relatively large diffusion coefficient into surrounding dielectrics such as silicon dioxide and into silicon. Copper from an interconnect may diffuse into the silicon dioxide layer causing the dielectric to become conductive while decreasing the dielectric strength of the silicon dioxide layer. Copper interconnects are therefore typically encapsulated by at least one diffusion barrier, comprising for instance silicon nitride, to prevent diffusion into the silicon dioxide layer. Copper is known to have low adhesive strength to various insulating layers, masking and etching a blanket layer of copper layer presents a challenge.
To provide a starting material for electroplating of a copper interconnect line to the surrounding layer of dielectric or insulation, a seed layer is typically deposited over the barrier layer. The invention addresses this aspect of the creation of copper interconnects and provides a method that allows the creation of such copper interconnects without the need for a separate barrier layer.
U.S. Pat. No. 6,333,560 B1 (Uzoh) shows a barrier-less copper interconnect process.
U.S. Pat. No. 6,124,198 (Moslehi) shows a barrier-less interconnect process.
U.S. Pat. No. 6,358,848 B1 (Lopatin) shows a Ca doped Cu seed layer.
U.S. Pat. No. 6,181,012 B1 (Edelstien et al.) shows a barrier-less copper process.
U.S. Pat. No. 6,090,710 (Andricacos et al.) and U.S. Pat. No. 5,969,422 (Ting et al.) are related copper interconnect patents.